FA Technology Roadmap
The purpose of the FA Technology Roadmap is to leverage the technical expertise captured throughout the industry to identify both current and future FA challenges as part of an annual industry-wide gap analysis. To have this effort formalized and available across the industry in an interactive and inclusive manner will not only return a critical compilation of relevant action items it will also serve as a recognized technical platform from which future failure analysts will benefit. In addition, its purpose is to serve as a technical platform from which everyone connected to the industry can learn, interact, and prepare for the future.
Die-Level Roadmap Council (DLRC) – Post-Isolation Domain
- Board Mentor – David Su, TSMC
- Chair – Vinod Narang, AMD
- Co-Chair – Chuan Zhang, NVIDIA
Categories | Top Gap Items |
Scanning Probe | A straightforward, robust, repeatable cross-section sample preparation process that will facilitate single plane analysis (topography, dopant) on specific, called out, 3-dimensional devices at the 14nm node and beyond. |
| A straightforward, robust, repeatable (plan-view and cross-section) sample preparation process that will facilitate high resolution tomographic analysis (topography, dopant) on specific, called out, 3-dimensional devices at the 14nm node and beyond. | |
| SSRM and SCM: Quantitative analysis of active dopants in sub-10nm features used in 3D device technologies, Availability of suitable calibration standards (Si, Poly, SiGe, & Jnxtns); Robust calibration methodology to allow extrapolation beyond std sample limits. | |
Circuit Edit | Current FIB Chip Edit tools are single beam systems. Imaging is destructive – causes sputter damage & implantation/amorphization. |
| Gas induced selective etching and material deposition (conductors & insulators) apparatus lacks positioning flexibility and gas flow regulation acuity. FIB gas chemistry has not advanced to keep pace with evolving semiconductor technology. | |
| Improvement of in-situ Optical Imaging system. IR imaging is essential for buried feature localization to enable the alignment of CAD. | |
Nanoprobing | New Device Architecture: Gate All Around, etc. |
| New Device Architecture: Backside PDN, Powervia, etc. | |
| Higher nano-probing volumes due to significant challenges with resolution in optical FI as well as the need to isolate a defect to an even smaller area in order to be able to physically root cause the defect. | |
| New nodes (3nm & beyond) require finer probes, Probe degradation faster with smaller tip size. Impacting probing efficiency at smaller nodes. | |
Microscopy | Solutions for ultra thin lamella preparation required for <5nm technologies. |
| In-situ delayering using Plasma-FIB still have challenges due the chip layout and metal lines density and thickness. Also the impacts of plasma beam on advanced nodes are not well documented | |
| For advanced process nodes with ultra low K dielectric and metal gate transistors, current Electron Beam capabilities on SEM and FIB systems are not capable of resolving small features. Resolution enhancements needed. | |
Sample Prep | Large area IC Delayering. No single tool has been demonstrated to cleanly delayer an IC over many layers in 3D transistor architecture. Need material removal control in the 10’s of nm’s if not 1’s of nm’s over >5mm diameter. |
| Heterogeneous Integration (HI). “Macro” sample prep. Quick, non-artifact sample preparation for delicate structures with widely differing materials. Optical modules and heterogeneously integrated devices often have soft polymers, hard metals, soft metals and hard/brittle materials all together. These devices need to be “cut down to size” ahead of more localized sample prep methods, then further prepared for imaging. | |
| Advanced techniques, BPR sample |
Die-Level Roadmap Council (DLRC) – Isolation Domain
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- Board Mentor – Keith Serrels, NXP
- Chair – Lesly Endrinal, Google
- Co-Chair – Szu Huat Goh, Chair Qualcomm
Focus Areas | Sub-Focus Areas (Description) | Outcome to achieve (KPI/Success Metric) | |
Laser-Based , Photon Emission and Thermal | 1 | CAD Alignment | CAD Alignment with 1 pixel precision for both PEM and LSM image overlay using recognizable features. Design for alignment |
| 2 | Laser probing resolution/crosstalk | single-few transistor/active resolution without invasiveness. 100nm spatial resolution with low invasiveness. Rise time of 200ps or better | |
| 3 | Pulsed visible laser stimulation | Resolution of 100nm, edge timing of 35ps, visible TRLADA | |
| 4 | SSPD array development | 1) 0.6V, 100us loops can be averaged within 1 min 2) An array of 10X10 pixels to spatially resolve a hotspot but it can be expanded. 3) movie mode with software hacks to manage the large dataset | |
| 5 | Signal quality on GAA is unclear. Sub-transistor resolution is impossible. | receive samples on GAA | |
| 6 | device backside power with a lot of speculation and lack of quality data | receive samples, and alignment towards which BPR scheme. | |
| 7 | photon emission resolution needs red shift for sensitivity, but this degrades resolution spatial | Detector development for high sensitivity (<0.5V), without loss in Spatial resolution | |
2D/2.5D/3D Package EFI | 1 | Test and Diagnostic Methodology (possible design insertions) for accurate localization of defects in 3D ICs | Ability to isolate 1) Die Vs Package fails, 2) TSVs and Interposers resistive/open defects 3) Within die defects Built-in Self-Test Utilize IEEE Standard Test Access |
| 2 | Pre-OFI Sample Prep: Direct line of sight access solution to mid-tier dies for Optical Fault Isolation | Develop repackaging solutions for mid-tier dies or interposer solutions | |
| 3 | OFI Challenge for F2F configuration in order to analyze bottom die in the presence of dense metal layers from the BEOL which will challenge laser stimulation, LVI/LVP, photon emissions. Analysis of the top die is straightforward, since the bulk silicon and active transistor region is in the line of sight of the OFI tool. | Solution to analyze bottom die | |
| 4 | Improve sensitivity and x,y,z resolution for magnetic field imaging to perform debug on thick 3DIC packages | Sensitivity of 500 nA Working distance (>100um) of GMR in mm range Achieve <250nm resolution Improve resolution in Z to sub micron. Improve sensitivity for detection of opens. | |
| 5 | Improve resolution for TDR (EOTPR). | x,y,z accuracy to less than 1um (currently it is at <5um) Less iterative approach to mprove accuracy and resolution for nested nets. | |
| 6 | OFI challenge for thin remaining silicon thickness (RST). What is the thermal implication? | Achieve (5μm<RST<40 μm) Minimize trade-offs like thermal implications | |
| 7 | OFI Challenge for Thermal Imaging. Improve X,Y, Z spatial resolution and increased sensitivity for multi stacked dies. | Resolution of < 1 um Improved sensitivity | |
System Level, Analog/RF and Digital Functional | 1 | standard of defect & fault models in analog and RF blocks | Realize EMMI/TIVA simulation image of analog blocks for design debug |
| 2 | how to compare real EMMI&TIVA&LVI image with simulation results, to realize a higher and finer localization with help of layout overlay, AI application? | correct position of detected EMMI/TIVA spot (shift ) of a single FET according to simulation results, | |
| 3 | SIL for dies in complex system board/ 3D Packagae/heavy doped power device | realize Z-direction localization with change the SIL focus in stacked dies or vertical power devices. | |
Product Yield Test and Diagnostics | 1 | SSN Diagnosis Enablement Complexity (data log collectin, diag setup management, consistency checks) | 1) A set of verified test methods from both Advantest and Teradyne that correctly logs the SSN fail cycle / instance information according to a published spec. 2) A set of tools that parses the tester generated fail logs and matches correctly against design collaterals with no ambiguity. 3) A workflow to verify the validity of the scan diagnosis output against design. |
| 2 | Embedded SRAM diagnosis validation | An end-to-end established workflow to thoroughly verify the embedded SRAM diagnosis work flow for large designs with huge number of embedded SRAM blocks of various types. | |
| 3 | Machine Learning & AI in Yield / Test Improvement | Established workflows to collect, analyze and present test data that involves sophisticated AI algorithms to address common product engineering issues like yield deviation, test time reduction and quality improvement. | |
General | 1 | EDA Support for EFI/EFA. EDA tools currently do not consider signal access or provide any assistance in aiding the design to improve signal access. Some times signal reconstruction is needed. Can EDA tools automatically insert features to facilitate this where possible? | EDA tools that, where possible, automatically insert features that improve probe access and ability to reconstruct signals. |
| 2 | Sample Prep Productivity Improvement. Sample-prep will be a productivity block, especially for EBP. Some combination of mechanical, dry + wet etch, laser, PFIB, and FIB will be required. What changes need to be made to sample prep tools to facilitate EFA/FI? CAD Nav across tools? Better integration between tools (something like FA4.0 initiatize with common sample holders, alignment features, etc)? | Ability to seamlessly move between the different sample preparation tools, including transfer of alignment points, use of compatible sample holders, and use of common image file formats including metadata. | |
| 3 | EBP ATE Docking Solution. SEM-based, 2nd generation EBP systems have limited sample volume and electrical access. It’s left up to the end user to work around these restrictions. Typically, this means that EBP-specific DUT cards must be designed for each product. Signaling and power delivery necessitates working with delicate vacuum side cabling and connectors. To reduce running costs and improve productivity, what’s needed is an EBP system that can directly dock to an ATE tester, similar to 1st generation commercial systems (e.g., Schlumberger IDS5000/10000). | E-beam prober that can dock to ATE w/o compromising SEM performance (maintain 10nm resolution). | |
| 4 | EBP Thermal Management Solution. New thermal solutions need to be developed for EBP since most existing DUT cooling schemes (e.g., air or liquid spray-cooling) are not vacuum compatible. SEM-based systems provide user-modifiable flanges that can accommodate liquid feedthroughs, but the rest is left up to the end user. An integrated thermal solution capable of dissipating 100W that induces low/no vibrations (i.e., levels that do not limit intrinsic EBP resolution (10nm)) and minimal drift (i.e., thermal equilibrium in <15minutes and drift levels compatible with EBP resolution and waveform acquisition times) is needed. | E-beam prober thermal solution capable of handling 100W that does not compromise SEM performance (maintain 10nm resolution). | |
| 5 | Thermo-Reflectance Capabilities Study. Need to determine capabilities of TR, especially with regards z-localization. Compared to LIT and SDL, the capabilities of TR are less understood. TR has lower SNR but potentially higher z-localization because it can operate at much higher frequencies. Q: Can TR distinguish between frontside and backside shorts? What about between individual frontside layers? What modifications can be made to CW-LVP system to optimize for thermal? Wavelength (given that thru-Si is no longer requirement)? Detector frequency response? There are different possible modes of operation: CW Frequency: modulate heat source at high frequency and use lock-in phase shift information. CW Time: look at thermal waveforms acquired with o-scope. Pulsed Time, Single-Point: Look at acquired thermal waveform. Pulsed Time, Area: Thermal ‘movies’. | Understand the capabilities and limitations of Thermo-reflectance, especially with regards z-resolution. | |
| 6 | Nanoprobing Methodology Study. Many open questions: How will frontside NP work when power rails are still intact? (Currently, deprocessing down to the contact level removes the power rails and allows individual transistors to be isolated and probed. This is no longer the case with BPR for all transistors.) Limited probe ampacity will restrict how large of a region can be powered through the probes. Can the DUT be biased through the (partially) intact substrate instead? Will nanoprobing systems need to be modified to provide biasing through the BGA substrate? How will frontside nanoprobing work if EFA/FI has already been performed from the backside (fill the created hole before frontside p-lapping)? | Understand the implications of having intact power rails on traditional nanoprobing. Is FIB editing to cut the rails from the frontside the answer? Understand whether alternate means for biasing the power rails is useful. | |
| 7 | Continued XADA Investigations: Continue feasibility studies. Develop optics for smaller spot size. System development. | Understand response of different types of devices to various X-ray beam parameters. Determine how and when XADA can be meaningfully applied. Determine practical limits of resolution and x-ray flux in a lab based system. Come up with system specs for vendors. | |
| 8 | Magnetic Field Mapping Investigation. Magnetic fields can penetrate most materials so new developments such as QDM and MOCI need to be investigated to see what role they may play. They promise to be lower cost and more robust than scanning squid, but have lower ultimate sensitivity. QDM offers ability to measure all three field components which may provide additional useful information. | Determine application space for new techniques. Compare/contrast to SQUID magnetometry. Determine spatial and temporal resolution limitations of each technique. | |
| 9 | Software Design Guideline Document. There may be new vendors coming in that have little experience with EFA/FI (X-ray, Magnetic field). Some are asking for guidance on U.I. Is it possible to standardize on the way to do cad alignment, move stage, save data, etc? Also, is it possible to standardize on image format and metadata (again, similar to FA4.0 initiative)? | Document with best practices for CAD alignment and navigation (CAD and Stage), software features required, Wizards, Image file formats and meta data | |
Package Innovation Roadmap Council (PIRC)
Focuses on industry related issues like tool robustness, sample challenges and working with AI.-
- Board Mentor – Felix Beaudoin, Global Foundries
- Chair – Christian Schmidt, NVIDIA
- Co-Chair – Yan Li, Samsung
Area |
Categories |
AI |
Collaborative learning & Training data standardization (Risks and challenges of cross company sharing) |
| Good vs bad image analysis | |
| Supporting Failure classification and recognition | |
Sample Size Challenge |
Sample size challenges for non-destructive Fault isolation imaging |
| 3D Navigation between high mag and overview images | |
| Sample size challenges for target preparation and material analysis | |
FA Tool Robustness |
General Tool Reliability |
| Global Supply Management | |
| Service and Support | |
| Green Energy |
FA Future Roadmap Council (FAFRC)
Mentor – Ryan Ross, Intel
Chair – Nicholas Antoniou, Prime Nano
How to Get Involved:
To learn more or to volunteer for the FA Technical Roadmap Committee, contact Nicole Hale at [email protected].FA Roadmap Committee
Keith Serrels
NXP Semiconductors
Committee Chair
Members
| Rohin Agny NXP | Jeff Gambino ON Semiconductor | Zhongling Qian Infineon AG | ||
| Brendan Foran The Aerospace Corporation | Szu Huat Goh Qualcomm | Wentao Qin Microchip Technology Inc. | ||
| Nicholas Antoniou PrimeNano Inc | Erwin Hendarto Silicon Labs | Venkat Krish Ravikumar AMD | ||
| Navid Asadi Zanjani University of Florida | Steven Herschbein GLOBALFOUNDRIES (Ret) | Renee Parente AMD | ||
| Nabil Bassim McMaster University | Nebojsa Jankovic NXP | Ryan Ross Intel | ||
| Felix Beaudoin, FASM GLOBALFOUNDRIES | Phil Kaszuba, FASM IBM (Ret) | Luc Saury Stmicroelectronics | ||
| Christian Boit, FASM Tech Univ Berlin | Eckhard Langer GLOBALFOUNDRIES | Christian Schmidt Nvidia | ||
| Jeremy Walraven Sandia | Juntao Li IBM | Jon Scholl Battelle | ||
| Samuel Chef Universite De Bourgogne | Yan Li Samsung Electronics Inc. | Keana Scott DOC/NIST | ||
| Jeongdong Choe TechInsights | Susan Li Infineon Technologies | Alan Street ams | ||
| Ed Cole FASM Sandia National Labs | William Lo NVIDIA | David Su TSMC (Ret) | ||
| Pradip Pichumani Meta | Vinod Narang AMD | Xianghong Tom Tong Intel | ||
| James Demarest FASM IBM | Baohua Niu TSMC Ltd. | Bryan Tracy Tesla | ||
| Kris Dickson NXP | Jochonia Nxumalo IBM | Martin Von Haartman Intel | ||
| Lesly Endrinal Google LLC | Rik Otte NXP | Bernice Zee AMD | ||
| Rommel Estores On Semiconductor | Yan Pan Microsoft | Chuan Zhang NVIDIA | ||
| Umberto Celano ASU | Sweta Pendyala Suny Poly / NY CREATES | Peng Li Intel |
Christian Hollerith
IFX
